A memory device having a three-dimensional structure has been proposed in which memory holes are made in a stacked body in which insulating layers are multiply stacked alternately with electrode layers that function as control gates of memory cells, and silicon bodies used to form channels are provided on the side walls of the memory holes with a charge storage film interposed between the silicon bodies and the side walls.
As the density of the memory holes is increased to increase the bit count per unit surface area, the requirements of the alignment precision between the memory holes and the slits that divide the electrode layers into pluralities are becoming even more stringent; and there is a fear of formation defects of the memory holes.
Although a method may be considered to simply make the memory holes and the slits simultaneously by lithography, the technical degree of difficulty is high; and in the current state of the art, it is difficult to ensure process margins.